1. Field of the Invention
This invention relates to a complementary type MOS integrated circuit device (hereinafter, referred to as a C-MOS IC) in which circuit is composed of N-channel type MOS field effect transistors (hereinafter, referred to as N-MOS FET's) and P-channel type MOS field effect transistors (hereinafter, referred to as P-MOS FET's), and more particularly to an improvement for preventing a latch-up phenomenon.
2. Description of the Prior Art
The C-MOS IC has an advantageous feature of consuming a very small power, but its fatal defect is the so-called latch-up phenomenon. The latch-up phenomenon lowers the impedance between power source terminals of the C-MOS IC chip to consume a very large power in the IC chip, with a result of a thermal breakdown of the IC chip.
This phenomenon will now be explained in more detail to some extent. The C-MOS IC has a well region of a conductivity type different from the conductivity type of the semiconductor substrate. In the well region and the substrate, MOS FET's of different channel types are respectively formed. Here, it is assumed to use P-type and N-type as the conductivity types of the well region and the substrate. The MOS FET's in the well region and the substrate are respectively N-channel type and P-channel type. The source region of the N-MOS FET, the well region and the substrate form a parasitic NPN bipolar transistor. The source region of the P-MOS FET, the substrate and the well region form a parasitic PNP bipolar transistor. The combination of these NPN and PNP bipolar transistors forms a parasitic PNPN thyristor.
The parasitic NPN bipolar transistor turns on in response to an application of noise to the drain of the N-MOS FET. The impedance component of the substrate, then, turns on the parasitic PNP transistor due to the collector current of the parasitic NPN transistor. The collector current of the PNP transistor is fed back to the NPN transistor so as to enhance the conductivity of the NPN transistor. As a result, the parasitic PNPN thyristor turns on to lower the impedance between the power source terminals electrically connected to the well region and the substrate.
The power source is applied to a P.sup.+ region formed in the well region through a bonding pad electrically connected thereto via a wiring layer on the IC chip. If the impedance of the wiring layer is small, the noise applied to the drain of the N-MOS FET causes a minority carrier injection into the emitter of the parasitic NPN transistor to turn on the same, but the collector current of the parasitic PNP transistor is effectively drained through the P.sup.+ region to the power source. The positive feedback of the collector current of the PNP transistor to the NPN transistor is restrained to prevent the parasitic PNPN thyristor from turning on.
However, since the wiring layer was connected with the limited portion of the P.sup.+ region in the prior art, some impedance was not avoidable in the wiring layer. This unavoidable impedance component allowed the positive feedback of the collector current of the parasitic PNP transistor to the parasitic NPN transistor, causing the turning-on of the parasitic PNPN thyristor. The turning-on condition cannot be reset to the cut-off condition so long as the power is continued to be supplied. Therefore, the latch-up phenomenon causes a thermal breakdown of the C-MOS IC.